This invention deals with integrated circuit manufacturing processes and structures, and in particular to a process and structure for testing the integrity of a barrier layer for Cu metallization structures.
As integrated circuit devices shrink, with semiconductor device geometries approaching 0.18 micron minimum feature size, and as circuit speed and performance increase, copper has replaced aluminum as the preferred electrical interconnect material. The use of copper as an interconnect material in silicon integrated circuits has occurred in response to the need for lowered interconnect resistivity, good electromigration resistance, and good deposition characteristics which allow effective filling of vias and contacts.
Copper metallization structures are often formed by a process known as Damascene, which is illustrated in FIG. 1a. An insulating layer known as the Interlevel Dielectric (ILD) separates metal layers in a multilevel metallization structure. ILD dielectric layer 2, which may be comprised of a bottom layer 4 and a top, low dielectric constant layer 6, has Damascene line regions 8 etched therein into which the metal lines will be inlaid. A barrier layer 10 is deposited, which serves to prevent diffusion of copper from the metal lines into the dielectric. This barrier layer is generally comprised of Ta or Ta compounds. A copper seed layer is then generally deposited, followed by an electroplated copper layer. The excess copper is then removed by a process known as Chemical Mechanical Polishing (CMP), leaving embedded copper lines 18, 20.
The integrity of the barrier layer 10 is critical to preventing diffusion of Cu into nearby dielectric or silicon regions. Diffused Cu in Si can cause degradation of device characteristics, such as leakage currents in reverse biased junctions. Cu defects in dielectrics can cause threshold voltage shifts and parasitic leakage currents. It is therefore essential to utilize methods for testing and/or monitoring barrier layer integrity. Barrier layer integrity tests can be utilized during development of barrier layer deposition processes, and they may be incorporated into manufacturing processes for monitoring during production.
In the prior art, barrier layer integrity has been evaluated by monitoring the line-to-line leakage current. In this method, unconnected, spaced apart copper lines are electrically stressed at higher electric field or temperature than would occur during normal circuit operation, and the leakage current between the lines is measured as an indication of copper diffusion through the barrier layer.
This prior art method for testing barrier layer integrity has inherent inaccuracies. Under temperature or voltage stress, Cu ions will diffuse across the lowest resistance path. The lowest resistance path may be a path which passes through the barrier layer, but it may instead be a path across the top dielectric surface, and accordingly falsely indicate lack of barrier layer integrity. In this prior art, a nitride capping layer 16 is generally deposited atop the Cu and dielectric surface to prevent the copper surface from oxidizing or corroding, and to isolate the copper line from the dielectric. One potential Cu diffusion path under stress is the nitride/dielectric interface. This effect is greatly magnified if conducting residues remain on the dielectric surface after CMP, due to incomplete polish or ineffective or insufficient post-CMP clean. Other sources of residues include improper processing of the nitride cap layer.
It is therefore an object of this invention to provide an improved structure and method for testing barrier integrity in an integrated circuit multilayer metallization structure.
It is a further object of this invention to provide a structure and method for testing barrier integrity which does not utilize measurement of line-to-line leakage current.
It is a further object ofthis invention to provide a structure and method for testing barrier integrity which is not subject to spurious leakage currents through paths other than through the barrier layer.
These objects are met by providing novel testing structures which provide a layer atop the dielectric layer and abutting the barrier layer, which has low permeability to copper. This low permeability layer, which may also be called a copper diffusion inhibitor layer, has copper permeability sufficiently low to inhibit copper from the metal lines or from conducting residues of the copper CMP from diffusing into the dielectric layer. The barrier layer integrity is then tested by performing CV or IV measurements across the ILD between the copper lines and the back of the silicon wafer.